From ae5bdb082da25d3f0fa59db22db17c00c741a4f4 Mon Sep 17 00:00:00 2001 From: Luke Wren Date: Tue, 9 May 2023 11:29:43 +0100 Subject: [PATCH] Reduce SWCLK frequency from SM/2 to SM/4, to reduce dead cycles. Also fix divider becoming 0 when extremely high SWCLK frequencies are requested (this would have been safe but you would get an extremely slow SWCLK). --- src/probe.c | 5 +++-- src/probe.pio | 25 ++++++++++++++----------- 2 files changed, 17 insertions(+), 13 deletions(-) diff --git a/src/probe.c b/src/probe.c index 6f544f0..b1d0d9d 100644 --- a/src/probe.c +++ b/src/probe.c @@ -62,8 +62,9 @@ static struct _probe probe; void probe_set_swclk_freq(uint freq_khz) { uint clk_sys_freq_khz = clock_get_hz(clk_sys) / 1000; picoprobe_info("Set swclk freq %dKHz sysclk %dkHz\n", freq_khz, clk_sys_freq_khz); - // Worked out with saleae - uint32_t divider = clk_sys_freq_khz / freq_khz / 2; + uint32_t divider = clk_sys_freq_khz / freq_khz / 4; + if (divider == 0) + divider = 1; pio_sm_set_clkdiv_int_frac(pio0, PROBE_SM, divider, 0); } diff --git a/src/probe.pio b/src/probe.pio index b176949..e3b2a25 100644 --- a/src/probe.pio +++ b/src/probe.pio @@ -39,6 +39,8 @@ // garbage on writes allows the interface code to return early after pushing a // write command, as there is no need in general to poll for a command's // completion as long as all commands are executed in order.) +// +// The SWCLK period is 4 PIO SM execution cycles. .program probe .side_set 1 opt @@ -46,22 +48,23 @@ public write_cmd: pull write_bitloop: - out pins, 1 side 0x0 ; Data is output by host on negedge - jmp x-- write_bitloop side 0x1 ; ...and captured by target on posedge - ; Fall through to next command + out pins, 1 [1] side 0x0 ; Data is output by host on negedge + jmp x-- write_bitloop [1] side 0x1 ; ...and captured by target on posedge + ; Fall through to next command .wrap_target public get_next_cmd: - pull side 0x0 ; SWCLK is initially low - out x, 8 ; Get bit count - out pindirs, 1 ; Set SWDIO direction - out pc, 5 ; Go to command routine + pull side 0x0 ; SWCLK is initially low + out x, 8 ; Get bit count + out pindirs, 1 ; Set SWDIO direction + out pc, 5 ; Go to command routine -public read_cmd: read_bitloop: - in pins, 1 side 0x1 ; Data is captured by host on posedge - jmp x-- read_bitloop side 0x0 + nop ; Additional delay on taken loop branch +public read_cmd: + in pins, 1 [1] side 0x1 ; Data is captured by host on posedge + jmp x-- read_bitloop side 0x0 push -.wrap ; Wrap to next command +.wrap ; Wrap to next command ; Implement probe_gpio_init() and probe_sm_init() methods here - set pins, offsets, sidesets etc