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Reduce SWCLK frequency from SM/2 to SM/4, to reduce dead cycles.

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Also fix divider becoming 0 when extremely high SWCLK frequencies
are requested (this would have been safe but you would get an
extremely slow SWCLK).
This commit is contained in:
Luke Wren
2023-05-09 11:29:43 +01:00
parent 491b96c1d4
commit ae5bdb082d
2 changed files with 17 additions and 13 deletions
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5
src/probe.c
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@@ -62,8 +62,9 @@ static struct _probe probe;
void probe_set_swclk_freq(uint freq_khz) {
uint clk_sys_freq_khz = clock_get_hz(clk_sys) / 1000;
picoprobe_info("Set swclk freq %dKHz sysclk %dkHz\n", freq_khz, clk_sys_freq_khz);
// Worked out with saleae
uint32_t divider = clk_sys_freq_khz / freq_khz / 2;
uint32_t divider = clk_sys_freq_khz / freq_khz / 4;
if (divider == 0)
divider = 1;
pio_sm_set_clkdiv_int_frac(pio0, PROBE_SM, divider, 0);
}

25
src/probe.pio
View File

@@ -39,6 +39,8 @@
// garbage on writes allows the interface code to return early after pushing a
// write command, as there is no need in general to poll for a command's
// completion as long as all commands are executed in order.)
//
// The SWCLK period is 4 PIO SM execution cycles.
.program probe
.side_set 1 opt
@@ -46,22 +48,23 @@
public write_cmd:
pull
write_bitloop:
out pins, 1 side 0x0 ; Data is output by host on negedge
jmp x-- write_bitloop side 0x1 ; ...and captured by target on posedge
; Fall through to next command
out pins, 1 [1] side 0x0 ; Data is output by host on negedge
jmp x-- write_bitloop [1] side 0x1 ; ...and captured by target on posedge
; Fall through to next command
.wrap_target
public get_next_cmd:
pull side 0x0 ; SWCLK is initially low
out x, 8 ; Get bit count
out pindirs, 1 ; Set SWDIO direction
out pc, 5 ; Go to command routine
pull side 0x0 ; SWCLK is initially low
out x, 8 ; Get bit count
out pindirs, 1 ; Set SWDIO direction
out pc, 5 ; Go to command routine
public read_cmd:
read_bitloop:
in pins, 1 side 0x1 ; Data is captured by host on posedge
jmp x-- read_bitloop side 0x0
nop ; Additional delay on taken loop branch
public read_cmd:
in pins, 1 [1] side 0x1 ; Data is captured by host on posedge
jmp x-- read_bitloop side 0x0
push
.wrap ; Wrap to next command
.wrap ; Wrap to next command
; Implement probe_gpio_init() and probe_sm_init() methods here - set pins, offsets, sidesets etc